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Rev 3; 10/07
Extremely Accurate I2C RTC with Integrated Crystal and SRAM
General Description
The DS3232 is a low-cost temperature-compensated crystal oscillator (TCXO) with a very accurate, temperature-compensated, integrated real-time clock (RTC) and 236 bytes of battery-backed SRAM. Additionally, the DS3232 incorporates a battery input and maintains accurate timekeeping when main power to the device is interrupted. The integration of the crystal resonator enhances the long-term accuracy of the device as well as reduces the piece-part count in a manufacturing line. The DS3232 is available in commercial and industrial temperature ranges, and is offered in an industry-standard 20-pin, 300-mil SO package. The RTC maintains seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Two programmable time-ofday alarms and a programmable square-wave output are provided. Address and data are transferred serially through an I2C bidirectional bus. A precision temperature-compensated voltage reference and comparator circuit monitors the status of VCC to detect power failures, to provide a reset output, and to automatically switch to the backup supply when necessary. Additionally, the RST pin is monitored as a pushbutton input for generating a reset externally.
Features
Accuracy 2ppm from 0C to +40C Accuracy 3.5ppm from -40C to +85C Battery Backup Input for Continuous Timekeeping Operating Temperature Ranges Commercial: 0C to +70C Industrial: -40C to +85C 236 Bytes of Battery-Backed SRAM Low-Power Consumption Real-Time Clock Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2099 Two Time-of-Day Alarms Programmable Square-Wave Output Fast (400kHz) I2C Interface 3.3V Operation Digital Temp Sensor Output: 3C Accuracy Register for Aging Trim RST Input/Output 300-Mil, 20-Pin SO Package Underwriters Laboratories (UL(R)) Recognized
DS3232
Ordering Information
PART DS3232S# TEMP RANGE 0C to +70C PINPACKAGE 20 SO TOP MARK DS3232
Applications
Servers Telematics Utility Power Meters GPS
DS3232SN# -40C to +85C 20 SO DS3232N # Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. Lead finish is JESD97 Category e3, and is compatible with both lead-based and lead-free soldering processes. A "#" anywhere on the top mark denotes a RoHS-compliant device.
Typical Operating Circuit
RPU = tR / CB VCC RPU RPU SCL SDA RST PUSHBUTTON RESET N.C. N.C. N.C. N.C. N.C. N.C. VCC INT/SQW 32kHz VBAT VCC VCC
Pin Configuration
TOP VIEW
N.C. 1 N.C. 2 32kHz 3 VCC 4 INT/SQW 5 RST 6 20 SCL 19 N.C. 18 SCL 17 SDA
CPU
DS3232
16 VBAT 15 GND 14 N.C. 13 N.C. 12 N.C. 11 N.C.
DS3232
GND
N.C. N.C. N.C. N.C. N.C.
N.C. 7 N.C. 8 N.C. 9 N.C. 10
SO
UL is a registered trademark of Underwriters Laboratories, Inc.
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST, INT/SQW Relative to Ground.............................-0.3V to +6.0V Operating Temperature Range (noncondensing) .............................................-40C to +85C Junction Temperature ......................................................+125C Storage Temperature Range ...............................-40C to +85C Lead Temperature (soldering, 10s) .....................................................+260C/10s Soldering Temperature (reflow, 2 times max) .......See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Supply Voltage Logic 1 Input SDA, SCL Logic 0 Input SDA, SCL Pullup Voltage (SDA, SCL, INT/SQW) SYMBOL VCC VBAT VIH VIL VPU VCC = 0V CONDITIONS MIN 2.3 2.3 0.7 x VCC -0.3 TYP 3.3 3.0 MAX 5.5 5.5 VCC + 0.3 +0.3 x VCC 5.5V UNITS V V V V
ELECTRICAL CHARACTERISTICS
(VCC = 2.3V to 5.5V, VCC = active supply (see Table 1), TA = -40C to +85C, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Active Supply Current SYMBOL ICCA CONDITIONS 32kHz output off (Notes 3, 4) I2C bus inactive, 32kHz output off, SQW output off (Note 4) I2C bus inactive, 32kHz output off, SQW output off VCC = 3.3V VCC = 5.5V VCC = 3.3V VCC = 5.5V VCC = 3.3V VCC = 5.5V 2.45 2.575 MIN TYP MAX 200 325 120 A 160 500 600 2.70 A V UNITS A
Standby Supply Current
ICCS
Temperature Conversion Current Power-Fail Voltage
ICCSCONV VPF
ACTIVE SUPPLY (Table 1 ) (2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted) (Note 1) Logic 1 Output, 32kHz I OH = -1mA I OH = -0.75mA I OH = -0.14mA Active supply > 3.3V, 3.3V > active supply > 2.7V, 2.7V > active supply > 2.3V
VOH
2.0
V
2
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.3V to 5.5V, VCC = active supply (see Table 1), TA = -40C to +85C, unless otherwise noted.) (Typical values are at VCC = 3.3V, VBAT = 3.0V, and TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER Logic 0 Output, INT/SQW, SDA Logic 0 Output, RST, 32kHz Output Leakage Current 32kHz, INT/SQW, SDA Input Leakage SCL RST Pin I/O Leakage TCXO Output Frequency Duty Cycle (Revision A3 Devices) Frequency Stability vs. Temperature Frequency Stability vs. Voltage Trim Register Frequency Sensitivity per LSB Temperature Accuracy Crystal Aging f/f OUT f/V f OUT VCC = 3.3V or VBAT = 3.3V 2.97V VCC < 3.63 0C to +40C VCC = 3.3V or VBAT = 3.3V VCC = 3.3V or VBAT = 3.3V -40C f/LSB Specified at: +25C +70C +85C Temp f/f0 VCC = 3.3V or VBAT = 3.3V After reflow, not production tested First year 0-10 years -3 1.0 5.0 -40C to 0C and +40C to +85C 31 -2 -3.5 1 0.7 0.1 0.4 0.8 +3 C ppm ppm 32.768 69 +2 +3.5 ppm ppm/V kHz % SYMBOL VOL VOL ILO ILI I OL RST high impedance (Note 5) I OL = 3mA I OL = 1mA Output high impedance -1 -1 -200 0 CONDITIONS MIN TYP MAX 0.4 0.4 +1 +1 +10 UNITS V V A A A
DS3232
ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Active Battery Current (Note 4) Timekeeping Battery Current (Note 4) Temperature Conversion Current Data-Retention Current SYMBOL IBATA CONDITIONS EOSC = 0, BBSQW = 0, SCL = 400kHz, BB32kHz = 0 EOSC = 0, BBSQW = 0, SCL = SDA = 0V, BB32kHz = 0, CRATE0 = CRATE1 = 0 VBAT = 3.3V VBAT = 5.5V VBAT = 3.4V VBAT = 5.5V 1.5 1.5 MIN TYP MAX 80 200 2.5 A 3.0 600 100 A nA UNITS A
IBAT
ITC IBATTC
EOSC = 0, BBSQW = 0, SCL = SDA = 0V EOSC = 1, SCL = SDA = 0V, +25C
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
AC ELECTRICAL CHARACTERISTICS
(Active supply (see Table 1) = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition (Note 6) Low Period of SCL Clock High Period of SCL Clock Data Hold Time (Notes 7, 8) Data Setup Time (Note 9) Start Setup Time Rise Time of Both SDA and SCL Signals (Note 10) Fall Time of Both SDA and SCL Signals (Note 10) Setup Time for STOP Condition Capacitive Load for Each Bus Line (Note 10) Capacitance for SDA, SCL Pulse Width of Spikes That Must Be Suppressed by the Input Filter Pushbutton Debounce Interface Timeout Reset Active Time Oscillator Stop Flag (OSF) Delay Temperature Conversion Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB CI/O tSP PBDB tIF tRST tOSF tCONV (Note 12) (Note 11) 25 250 100 125 200 10 30 250 35 Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode CONDITIONS MIN 100 0.04 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 0.6 4.7 400 300 1000 300 300 0.9 0.9 25,000 25,000 TYP MAX 400 100 UNITS kHz s s s s s ns s ns ns s pF pF ns ms ms ms ms ms
POWER-SWITCH CHARACTERISTICS
(TA = -40C to +85C)
PARAMETER VCC Fall Time; VPF(MAX) to VPF(MIN) VCC Rise Time; VPF(MIN) to VPF(MAX) Recovery at Power-Up SYMBOL tVCCF tVCCR tREC (Note 13) CONDITIONS MIN 300 0 125 300 TYP MAX UNITS s s ms
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
Pushbutton Reset Timing
RST
DS3232
PBDB
tRST
Power-Switch Timing
VCC VPF(MAX) VPF(MIN) VPF VPF
tVCCF
tVCCR
tREC
RST
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Data Transfer on I2C Serial Bus
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. ICCA--SCL clocking at max frequency = 400kHz. Current is the averaged input current, which includes the temperature conversion current. The RST pin has an internal 50k (nominal) pullup resistor to VCC. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB--total capacitance of one bus line in pF. Note 11: Minimum operating frequency of the I2C interface is imposed by the timeout period. Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0V VCC VCC(MAX) and 2.3V VBAT 3.4V. Note 13: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately goes high. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS3232 toc01
DS3232
SUPPLY CURRENT vs. SUPPLY VOLTAGE
VCC = 0V BB32kHz = 0 BBSQW = 0 BSY = 0
DS3232 toc02
150 SCL = SDA = VCC 125 SUPPLY CURRENT (nA) 100 75 50 25 0 2.3 2.8 3.3 3.8 VCC (V) 4.3 4.8 5.3 RST ACTIVE
1000 950 SUPPLY CURRENT (nA) 900 850 800 750 700 2.3 2.8 3.3 3.8 VBAT (V) 4.3 4.8 5.3
SUPPLY CURRENT vs. TEMPERATURE
DS3232 toc03
FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING
65 55 45 35 25 15 5 -5 -15 -25 -35 AGING = +127 AGING = +32 -40 -20 0 20 40 TEMPERATURE (C) 60 80
DS3232 toc04
0.900 VCC = 0V BB32kHz = 0 VBAT = 3.4V SUPPLY CURRENT (A) 0.800 VBAT = 3.0V
75 AGING = -128 AGING = -33 AGING = 0
0.700
0.600 -40 -20 0 20 40 TEMPERATURE (C) 60 80
FREQUENCY DEVIATION (ppm)
-45
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Block Diagram
VCC
X1
OSCILLATOR AND CAPACITOR ARRAY CONTROL LOGIC/ DIVIDER PUSHBUTTON RESET; SQUARE-WAVE BUFFER; INT/SQW CONTROL N
RST
X2
32kHz
DS3232
VCC VBAT GND POWER CONTROL TEMPERATURE SENSOR CONTROL AND STATUS REGISTERS N INT/SQW
SRAM SCL I2C INTERFACE AND ADDRESS REGISTER DECODE SDA CLOCK AND CALENDAR REGISTERS USER BUFFER (7 BYTES)
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
Pin Description
PIN 1, 2, 7-14, 19 3 4 NAME N.C. 32kHz VCC FUNCTION No Connection. Not connected internally. Must be connected to ground. 32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin will be low. DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1F to 1.0F capacitor.
DS3232
5
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2 and INT/SQW RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled. Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST pin is driven high impedance. The active-low, open-drain output is combined with a debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50k nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the crystal oscillator is disabled, tRST is bypassed and RST immediately goes high. Ground Backup Power-Supply Input. This pin should be decoupled using a 0.1F to 1.0F low-leakage capacitor. If the I2C interface is inactive whenever the device is powered by the VBAT input, the decoupling capacitor is not required. If VBAT is not used, connect to ground. Diodes placed in series between the VBAT pin and the battery can cause improper operation. UL recognized to ensure against reverse charging when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul. Serial-Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. Serial-Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data movement on the serial interface. A connection to only one of the pins is required. The other pin must be connected to the same signal or be left floating.
6
RST
15
GND
16
VBAT
17
SDA
18, 20
SCL
Detailed Description
The DS3232 is a serial RTC driven by a temperaturecompensated 32kHz crystal oscillator. The TCXO provides a stable and accurate reference clock, and maintains the RTC to within 2 minutes per year accuracy from -40C to +85C. The TCXO frequency output is available at the 32kHz pin. The RTC is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW provides either an interrupt signal due to alarm conditions or a square-wave output. The clock/calendar provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I2C bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of VCC to detect power failures and to automatically switch to the backup supply when necessary. The RST pin provides an external pushbutton function and acts as an indicator of a power-fail event. Also available are 236 bytes of general-purpose battery-backed SRAM.
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Operation
The block diagram shows the main elements of the DS3232. The eight blocks can be grouped into four functional groups: TCXO, power control, pushbutton function, and RTC. Their operations are described separately in the following sections. After the internal timer has expired (PBDB), the DS3232 continues to monitor the RST line. If the line is still low, the DS3232 continuously monitors the line looking for a rising edge. Upon detecting release, the DS3232 forces the RST pin low and holds it low for tRST. The same pin, RST, is used to indicate a power-fail condition. When VCC is lower than VPF, an internal powerfail signal is generated, which forces the RST pin low. When VCC returns to a level above VPF, the RST pin is held low for tREC to allow the power supply to stabilize. If the oscillator is not running (see the Power Control section) when VCC is applied, tREC is bypassed and RST immediately goes high. Assertion of the RST output, whether by pushbutton or power-fail detection, does not affect the internal operation of the DS3232.
32kHz TCXO
The temperature sensor, oscillator, and control logic form the TCXO. The controller reads the output of the on-chip temperature sensor and uses a lookup table to determine the capacitance required, adds the aging correction in AGE register, and then sets the capacitance selection registers. New values, including changes to the AGE register, are loaded only when a change in the temperature value occurs. The temperature is read on initial application of VCC and once every 64 seconds (default, see the description for CRATE1 and CRATE0 in the control/status register) afterwards.
Real-Time Clock
With the clock source from the TCXO, the RTC provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The clock provides two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW pin either generates an interrupt due to alarm condition or outputs a square-wave signal and the selection is controlled by the bit INTCN.
Power Control
This function is provided by a temperature-compensated voltage reference and a comparator circuit that monitors the VCC level. When VCC is greater than VPF, the part is powered by VCC. When VCC is less than VPF but greater than VBAT, the DS3232 is powered by VCC. If V CC is less than V PF and is less than V BAT , the device is powered by VBAT. See Table 1.
Table 1. Power Control
SUPPLY CONDITION VCC < VPF, VCC < VBAT VCC < VPF, VCC > VBAT VCC > VPF, VCC < VBAT VCC > VPF, VCC > VBAT POWERED BY VBAT VCC VCC VCC
SRAM
The DS3232 provides 236 bytes of general-purpose battery-backed read/write memory. The I2C address ranges from 14h to 0FFh. The SRAM can be written or read whenever VCC or VBAT is greater than the minimum operating voltage.
To preserve the battery, the first time VBAT is applied to the device, the oscillator does not start up and no temperature conversions take place until VCC exceeds VPF or until a valid I2C address is written to the part. After the first time VCC is ramped up, the oscillator starts up and the V BAT source powers the oscillator during power-down and keeps the oscillator running. When the DS3232 switches to VBAT, the oscillator may be disabled by setting the EOSC bit.
Address Map
Figure 1 shows the address map for the DS3232 timekeeping registers. During a multibyte access, when the address pointer reaches the end of the register space (0FFh), it wraps around to location 00h. On an I 2C START or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case the main registers update during a read.
Pushbutton Reset Function
The DS3232 provides for a pushbutton switch to be connected to the RST output pin. When the DS3232 is not in a reset cycle, it continuously monitors the RST signal for a low going edge. If an edge transition is detected, the DS3232 debounces the switch by pulling the RST low.
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I2C Interface
The I2C interface is accessible whenever either VCC or VBAT is at a valid level. If a microcontroller connected to the DS3232 resets because of a loss of VCC or other
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Figure 1. Address Map for DS3232 Timekeeping Registers and SRAM
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h-0FFh A1M1 A1M2 A1M3 A1M4 A2M2 A2M3 A2M4 EOSC OSF SIGN SIGN DATA 0 x 12/24 DY/DT BBSQW DATA DATA DATA 0 x 12/24 DY/DT BIT 7 MSB 0 0 0 0 0 Century 12/24 0 0 0 10 Year 10 Seconds 10 Minutes AM/PM 10 Hour 10 Hour 0 BIT 6 BIT 5 10 Seconds 10 Minutes AM/PM 10 Hour 0 10 Date 10 Month 10 Hour 0 0 Date Month Year Seconds Minutes Hour Day Date Minutes 10 Hour Hour Day Date RS1 EN32kHz DATA DATA 0 0 x INTCN BSY DATA DATA 0 0 x A2IE A2F DATA DATA 0 0 x A1IE A1F DATA DATA 0 0 x BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LSB FUNCTION Seconds Minutes Hours Day Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Alarm 1 Hours Alarm 1 Day Alarm 1 Date Alarm 2 Minutes Alarm 2 Hours Alarm 2 Day Alarm 2 Date Control Control/Status Aging Offset MSB of Temp LSB of Temp Not used SRAM RANGE 00-59 00-59 1-12 + AM/PM 00-23 1-7 1-31 01-12 + Century 00-99 00-59 00-59 1-12 + AM/PM 00-23 1-7 1-31 00-59 1-12 + AM/PM 00-23 1-7 1-31 -- -- -- -- -- Reserved for test 00h-0FFh
Seconds Minutes Hour
10 Date 10 Minutes AM/PM 10 Hour
10 Date CONV DATA DATA 0 0 x RS2 CRATE0 DATA DATA 0 0 x
BB32kHz CRATE1
Note: Unless otherwise specified, the registers' state is not defined when power is first applied.
event, it is possible that the microcontroller and DS3232 I2C communications could become unsynchronized, e.g., the microcontroller resets while reading data from the DS3232. When the microcontroller resets, the DS3232 I2C interface may be placed into a known state by toggling SCL until SDA is observed to be at a high level. At that point the microcontroller should pull SDA low while SCL is high, generating a START condition. If SCL is held low for greater than tIF, the internal I2C interface is reset. This limits the minimum frequency at which the I 2C interface can be operated. If data is
being written to the device when the interface timeout is exceeded, prior to the acknowledge, the incomplete byte of data is not written.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. Figure 1 illustrates the RTC registers. The time and calendar data are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in binary-coded decimal (BCD) format. The DS3232 can be run in either 12-hour or 24-hour mode. Bit 6 of the
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
hours register is defined as the 12- or 24-hour mode select bit. When high, 12-hour mode is selected. In 12hour mode, bit 5 is the AM/PM bit with logic-high being PM. In 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). The century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START and when the register pointer rolls over to zero. The time information is read from these secondary registers, while the clock continues to run. This eliminates the need to reread the registers in case the main registers update during a read. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge from the DS3232. Once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running.
Alarms
The DS3232 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. The alarms can be programmed (by the alarm enable and INTCN bits of the control register) to activate the INT/SQW output on an alarm match condition. Bit 7 of each of the time-ofday/date alarm registers are mask bits (Table 2). When all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers match the corresponding values stored in the time-ofday/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 2 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm will be the result of a match with date of the month. If DY/DT is written to logic 1, the alarm will be the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding Alarm Flag `A1F' or `A2F' bit is set to logic 1. If the corresponding Alarm Interrupt Enable `A1IE' or `A2IE' is also set to logic 1 and the INTCN bit is set to logic 1, the alarm condition activates the INT/SQW signal. The match is tested on the onceper-second update of the time and date registers.
Table 2. Alarm Mask Bits
DY/DT X X X X 0 1 ALARM 1 REGISTER MASK BITS (BIT 7) A1M4 1 1 1 1 0 0 A1M3 1 1 1 0 0 0 A1M2 1 1 0 0 0 0 A1M1 1 0 0 0 0 0 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match
DY/DT X X X 0 1
ALARM 2 REGISTER MASK BITS (BIT 7) A2M4 1 1 1 0 0 A2M3 1 1 0 0 0 A2M2 1 0 0 0 0
ALARM RATE Alarm once per minute (00 seconds of every minute) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
Control Register (0Eh)
BIT 7 NAME: POR*: EOSC 0 BIT 6 BBSQW 0 BIT 5 CONV 0 BIT 4 RS2 1 BIT 3 RS1 1 BIT 2 INTCN 1 BIT 1 A2IE 0 BIT 0 A1IE 0
DS3232
*POR is defined as the first application of power to the device, either VBAT or VCC.
Special-Purpose Registers
The DS3232 has two additional registers (control and control/status) that control the real-time clock, alarms, and square-wave output.
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped when the DS3232 switches to battery power. This bit is clear (logic 0) when power is first applied. When the DS3232 is powered by VCC, the oscillator is always on regardless of the status of the EOSC bit. Bit 6: Battery-Backed Square-Wave Enable (BBSQW). When set to logic 1 and the DS3232 is being powered by the VBAT pin, this bit enables the square-wave output or interrupt when VCC is absent. When BBSQW is logic 0, the INT/SQW pin goes high impedance when VCC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bit 5: Convert Temperature (CONV). Setting this bit to 1 forces the temperature sensor to convert the temperature into digital code and execute the TCXO algorithm to update the capacitance array to the oscillator. This can only happen when a conversion is not already in progress. The user should check the status bit BSY before forcing the controller to start a new TCXO execution. A user-initiated temperature conversion does not affect the internal 64-second (default interval) update cycle. A user-initiated temperature conversion does not affect the BSY bit for approximately 2ms. The CONV bit remains at a 1 from the time it is written until the conversion is finished, at which time both CONV and BSY go to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The following table shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (8.192kHz) when power is first applied. SQUARE-WAVE OUTPUT FREQUENCY
RS2 0 0 1 1 RS1 0 1 0 1 SQUARE-WAVE OUTPUT FREQUENCY 1Hz 1.024kHz 4.096kHz 8.192kHz
Bit 2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When the INTCN bit is set to logic 0, a square wave is output on the INT/SQW pin. When the INTCN bit is set to logic 1, a match between the timekeeping registers and either of the alarm registers activates the INT/SQW (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to logic 1 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the INT/SQW signal. The A1IE bit is disabled (logic 0) when power is first applied.
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Control/Status Register (0Fh)
BIT 7 NAME: POR*: OSF 1 BIT 6 BB32kHz 1 BIT 5 CRATE1 0 BIT 4 CRATE0 0 BIT 3 EN32kHz 1 BIT 2 BSY 0 BIT 1 A2F 0 BIT 0 A1F 0
*POR is defined as the first application of power to the device, either VBAT or VCC.
Control/Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both VCC and VBAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. Bit 6: Battery-Backed 32kHz Output (BB32kHz). This bit enables the 32kHz output when powered from VBAT (provided EN32kHz is enabled). If BB32kHz = 0, the 32kHz output is low when the part is powered by VBAT. Bits 5 and 4: Conversion Rate (CRATE1 and CRATE0). These two bits control the sample rate of the TCXO. The sample rate determines how often the temperature sensor makes a conversion and applies compensation to the oscillator. Decreasing the sample rate decreases the overall power consumption by decreasing the frequency at which the temperature sensor operates. However, significant temperature changes that occur between samples may not be completely compensated for, which reduce overall accuracy. When a new conversion rate is written to the register, it may take up to the new conversion rate time before the conversions occur at the new rate.
SAMPLE RATE (seconds) 64 128 256 512
Bit 3: Enable 32kHz Output (EN32kHz). This bit indicates the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes low. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a power source is applied to the DS3232 (if the oscillator is running). Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the conversion is complete. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT/SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
CRATE1 0 0 1 1
CRATE0 0 1 0 1
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
Aging Offset (10h)
BIT 7 NAME: POR*: SIGN 0 BIT 6 DATA 0 BIT 5 DATA 0 BIT 4 DATA 0 BIT 3 DATA 0 BIT 2 DATA 0 BIT 1 DATA 0 BIT 0 DATA 0
DS3232
Temperature Register (Upper Byte) (11h)
BIT 7 NAME: POR*: SIGN 0 BIT 6 DATA 0 BIT 5 DATA 0 BIT 4 DATA 0 BIT 3 DATA 0 BIT 2 DATA 0 BIT 1 DATA 0 BIT 0 DATA 0
Temperature Register (Lower Byte) (12h)
BIT 7 NAME: POR*: DATA 0 BIT 6 DATA 0 BIT 5 0 0 BIT 4 0 0 BIT 3 0 0 BIT 2 0 0 BIT 1 0 0 BIT 0 0 0
SRAM (14h-FFh)
BIT 7 NAME: POR*: D7 X BIT 6 D6 X BIT 5 D5 X BIT 4 D4 X BIT 3 D3 X BIT 2 D2 X BIT 1 D1 X BIT 0 D0 X
*POR is defined as the first application of power to the device, either VBAT or VCC.
Aging Offset Register
The aging offset register provides an 8-bit code to add to or subtract from the oscillator capacitor array. The data is encoded in two's complement, with bit 7 representing the sign bit. One LSB represents the smallest capacitor to be switched in or out of the capacitance array at the crystal pins. The offset register is added to the capacitance array during a normal temperature conversion, if the temperature changes from the previous conversion, or during a manual user conversion (setting the CONV bit). To see the effects of the aging register on the 32kHz output frequency immediately, a manual conversion should be started after each aging offset register change. Positive aging values add capacitance to the array, slowing the oscillator frequency. Negative values remove capacitance from the array, increasing the oscillator frequency. The change in ppm per LSB is different at different temperatures. The frequency vs. temperature curve is shifted by the values used in this register. At +25C, one LSB typically provides about 0.1ppm change in frequency.
Temperature Registers (11h-12h)
Temperature is represented as a 10-bit code with a resolution of +0.25C and is accessible at location 11h and 12h. The temperature is encoded in two's complement format, with bit 7 in the MSB representing the sign bit. The upper 8 bits are at location 11h and the lower 2 bits are in the upper nibble at location 12h. Upon power reset, the registers are set to a default temperature of 0C and the controller starts a temperature conversion. New temperature readings are stored in this register.
I2C Serial Data Bus
The DS3232 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is defined as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS3232 operates as a slave on the I2C bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS3232 works in both modes.
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 2. I2C Data Transfer Overview
The following bus protocol has been defined (Figure 2): * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and
the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 3 and 4 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first.
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM
ADDRESS> S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P S = START DATA TRANSFERRED A = ACKNOWLEDGE (X + 1 BYTES + ACKNOWLEDGE) P = STOP R/W = READ/WRITE OR DIRECTION BIT SLAVE ADDRESS + R/W BIT = D0H
Figure 3. Slave Receiver Mode (Write Mode)
ADDRESS> S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P DATA TRANSFERRED S = START (X + 1 BYTES + ACKNOWLEDGE) A = ACKNOWLEDGE NOTE: LAST DATA BYTE IS FOLLOWED BY P = STOP A NOT ACKNOWLEDGE (A) SIGNAL A = NOT ACKNOWLEDGE R/W = READ/WRITE OR DIRECTION BIT SLAVE ADDRESS + R/W BIT = D1H
Figure 4. Slave Transmitter Mode (Read Mode)
Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS3232 can operate in the following two modes: Slave receiver mode (DS3232 write mode): Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS3232 address,
which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. After the DS3232 acknowledges the slave address + write bit, the master transmits a word address to the DS3232. This sets the register pointer on the DS3232, with the DS3232 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS3232 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (DS3232 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3232 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS3232 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS3232 outputs an acknowledge on SDA. The DS3232 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS3232 must receive a not acknowledge to end a read.
DS3232

Handling, PC Board Layout, and Assembly
The DS3232 package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground.
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Extremely Accurate I2C RTC with Integrated Crystal and SRAM DS3232
Chip Information
TRANSISTOR COUNT: 48,000 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Theta-JA: +55.1C/W Theta-JC: +24C/W
Thermal Information
Package Information
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PACKAGE TYPE 20 SO DOCUMENT NO. 56-G4009-001
Revision History
Pages changed at Rev 1: 1 Pages changed at Rev 2: 1, 4, 7, 11, 14, 17 Pages changed at Rev 3: 1, 3, 9, 10, 11, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Dallas Semiconductor Corporation. is a registered trademark of Maxim Integrated Products, Inc.
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